 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| FeaTures n n n n n n n LTC3860 Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Current Sharing DescripTion The LTC(R)3860 is a dual, PolyPhase(R) synchronous stepdown switching regulator controller for high current distributed power systems, digital signal processors, and other telecom and industrial DC/DC power supplies. It uses a constant frequency voltage mode architecture combined with very low offset, high bandwidth error amplifiers and a remote output sense differential amplifier for excellent transient response and output regulation. The controller incorporates lossless inductor DCR current sensing to maintain current balance between phases and to provide overcurrent protection. The chip operates from a VCC supply between 3V and 5.5V and is designed for stepdown conversion from VIN between 3V and 24V to output voltages between 0.6V and VCC - 0.5V. The TRACK/SS pins provide programmable soft-start or tracking functions. Inductor current reversal is disabled during soft-start to safely power prebiased loads. The constant operating frequency can be synchronized to an external clock or linearly programmed from 250kHz to 1.25MHz. Up to six LTC3860 controllers can operate in parallel for 1-, 2-, 3-, 4-, 6- or 12-phase operation. The LTC3860 is available in a 32-pin 5mm x 5mm QFN package. L, LT, LTC, LTM, PolyPhase, Module, Linear Technology and the Linear logo are registered trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6144194, 5055767 n n n n n n n n Constant Frequency Voltage Mode Control with Accurate Current Sharing 0.75% 0.6V Voltage Reference Differential Remote Output Voltage Sense Amplifier Multiphase Capability--Up to 12-Phase Operation Programmable Current Limit Safely Powers a Pre-Biased Load Programmable or PLL-Synchronizable Switching Frequency Up to 1.25MHz Lossless Current Sensing Using Inductor DCR or Precision Current Sensing with Sense Resistor Fast and Accurate True Operational Error Amplifiers VCC Range: 3V to 5.5V VIN Range: 3V to 24V Power Good Output Voltage Monitor Output Voltage Tracking Capability Programmable Soft-Start Available in a 32- Pin 5mm x 5mm QFN Package applicaTions n n n n High Current Distributed Power Systems Digital Signal Processor and ASIC Supplies Telecom Systems Industrial Power Supplies Typical applicaTion PWM1 VIN VCC 470F PWM1 VINSNS VCC FREQ FB2 ILIM2 LTC3860 FB1 COMP1,2 SS1,2 VSNSOUT VSNSN VSNSP SGND VCC 1F VOUT 1nF 20k 20k 220 33pF 0.1F 12.7k RUN1,2 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P 50k 0.22F 0.22F PWM2 VCC 100pF LTC4449 IN GND VLOGIC TG VCC TS BOOST BG 0.22F VIN TG1 SW1 BG1 2.32k VOUT 1.2V 330F 50A 4 2.32k 0.3H 3860 TA01 0.3H VIN LTC4449 IN GND VLOGIC TG VCC TS BOOST BG 0.22F TG2 SW2 BG2 PWM2 IAVG CLKIN 220pF 3860f LTC3860 absoluTe maximum raTings (Note 1) pin conFiguraTion TRACK/SS1 PWMEN1 PWMEN2 TOP VIEW PGOOD1 VINSNS SGND SGND IAVG PWM1 24 RUN1 23 ILIM1 22 ISNS1P 33 SGND 21 ISNS1N 20 ISNS2N 19 ISNS2P 18 ILIM2 17 RUN2 9 10 11 12 13 14 15 16 TRACK/SS2 CLKOUT PHSMD PGOOD2 PWM2 FREQ CLKIN VCC Voltage .................................................. -0.3V to 6V VINSNS Voltage ......................................... -0.3V to 30V VSNSN Voltage ............................................ -0.3V to 2V RUN Voltage ................................................ -0.3V to 6V ISNS1P , ISNS1N, ISNS2P , ISNS2N ...........................-0.3V to (VCC + 0.1V) All Other Voltages .........................-0.3V to (VCC + 0.3V) Operating Junction Temperature Range (Note 3) LTC3860E............................................. -40C to 85C LTC3860I............................................ -40C to 125C Storage Temperature Range................... -65C to 125C 32 31 30 29 28 27 26 25 VCC 1 FB1 2 COMP1 3 VSNSOUT 4 VSNSN 5 VSNSP 6 COMP2 7 FB2 8 UH PACKAGE 32-LEAD (5mm 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB orDer inFormaTion LEAD FREE FINISH LTC3860EUH#PBF LTC3860IUH#PBF TAPE AND REEL LTC3860EUH#TRPBF LTC3860IUH#TRPBF PART MARKING* 3860 3860 PACKAGE DESCRIPTION 32-Lead (5mm x 5mm) Plastic QFN 32-Lead (5mm x 5mm) Plastic QFN TEMPERATURE RANGE -40C to 85C -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elecTrical characTerisTics SYMBOL VCC VIN IQ PARAMETER Input Voltage Range VIN Range Input Voltage Supply Current Normal Operation Shutdown Mode UVLO RUN Input Threshold RUN Input Pull-Up Current Undervoltage Lockout Threshold Soft-Start Pin Output Current The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V, fOSC = 0.6MHz unless otherwise specified. CONDITIONS l MIN 3.0 3 l TYP MAX 5.5 24 UNITS V V mA A mA V mV s V mV A 3860f VCC = 5V VRUN1,2 = 5V VRUN1,2 = 0V VCC < VUVLO VRUN Rising VRUN Hysteresis VRUN1,2 = TBDV VCC Rising VCC Hysteresis VSS = 0V 14 3.5 1.95 2.25 250 1.5 l 50 2.45 VRUN IRUN VUVLO ISS 100 2.5 3.0 LTC3860 elecTrical characTerisTics SYMBOL tSS(INTERNAL) VFB VFB/VCC ILIMIT Power Good VFB(OV) VFB(UV) VPGOOD(ON) Error Amplifier IFB IOUT AV(OL) SR f0dB AV VOS SR f0dB VOUT(MAX) VISENSE(MAX) AV(ISENSE) VCM(ISENSE) IISENSE VMM fOSC FB Pin Input Current COMP Pin Output Current Open-Loop Voltage Gain Slew Rate COMP Unity-Gain Bandwidth Diffierential Amplifier Voltage Gain Input Referred Offset Slew Rate Bandwidth Maximum Output Voltage Maximum Differential Current Sense Voltage (VISNSP-VISNSN) Voltage Gain Input Common Mode Range SENSE Pin Input Current Current Sense Mismatch Oscillator Frequency VCM = 1.5V Channel 1 to Channel 2 VCLKIN = 0V VFREQ = 0V VFREQ = 5V VCLKIN = 5V RFREQ < 24.9k RFREQ = 30.1k RFREQ = 54.9k RFREQ = 75.0k Maximum Frequency Minimum Frequency IFREQ tCLKIN(HI) FREQ Pin Output Current CLKIN Pulse Width High VFREQ = 0.8V VCLKIN = 0V to 5V 1.25 19 100 20 l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V, fOSC = 0.6MHz unless otherwise specified. PARAMETER Internal Soft-Start Time Regulated Feedback Voltage Regulated Feedback Voltage Line Dependence ILIM Pin Output Current PGOOD/VFB Overvoltage Threshold PGOOD/VFB Undervoltage Threshold PGOOD Pull-Down Resistance VFB = 600mV Sourcing Sinking -100 1 5 75 45 20 VVSNSN = 0V VVSNSN = 0V l CONDITIONS 0C to 85C TJ -40C to 125C TJ 3.0V < VCC < 5.5V VILIM = 0.8V VFB Falling VFB Rising VFB Falling VFB Rising MIN 595.5 594 TYP 2 600 600 0.05 MAX 604.5 606 0.2 22 UNITS ms mV mV %/V A mV mV mV mV nA mA mA dB V/s MHz l 18 20 645 660 540 555 15 650 530 670 550 60 100 Differential Amplifier 1.005 -2 45 20 4 50 18.5 -0.3 100 -2.75 2.75 VCC + 0.1 1 0.995 2 V/V mV V/s MHz V mV V/V V nA mV Current Sense Amplifier Oscillator and Phase-Locked Loop l l 360 540 400 600 200 300 800 1.2 440 660 kHz kHz kHz kHz kHz MHz 0.25 21 MHz MHz A ns 3860f LTC3860 elecTrical characTerisTics SYMBOL tCLKIN(LO) RCLKIN VCLKIN VFREQ VOL(CLKOUT) VOH(CLKOUT) 2-1 CLKOUT-1 PARAMETER CLKIN Pulse Width Low CLKIN Pull-Up Resistance CLKIN Input Threshold FREQ Input Threshold VCLKIN Falling VCLKIN Rising VCLKIN = 0V VFREQ Falling VFREQ Rising ILOAD = -500A ILOAD = 500A The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V, fOSC = 0.6MHz unless otherwise specified. CONDITIONS VCLKIN = 0V to 5V MIN 100 13 1.2 2 1.5 2.5 0.2 VCC - 0.2 180 180 120 60 90 240 l l TYP MAX UNITS ns k V V V V V V Deg Deg Deg Deg Deg Deg V CLKOUT Low Output Voltage CLKOUT High Output Voltage Channel 1-to-Channel 2 Phase Relationship VPHSMD = 0V VPHSMD = Float VPHSMD = VCC CLKOUT-to-Channel 1 Phase Relationship VPHSMD = 0V VPHSMD = Float VPHSMD = VCC ILOAD = 500A ILOAD = -500A 4.5 PWM/PWMEN Outputs PWM PWM Output High Voltage PWM Output Low Voltage PWM Output Current in Hi-Z State PWM Maximum Duty Cycle PWMEN PWMEN Output High Voltage ILOAD = 1mA l 0.5 5 91.5 4.5 V A % V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * JA) Note 3: The LTC3860E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3860I is guaranteed over the full -40C to 125C operating junction temperature range. The maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistors and other environmental factors. Typical perFormance characTerisTics Load Step Transient Response (Single Phase) ILOAD 10A/DIV IL 10A/DIV VOUT 50mV/DIV VIN = 12V 50s/DIV VOUT = 1.2V ILOAD STEP = 10A COMP VALUES: R2A = 6.8k , C1A = 470pF C2A = 100pF , 3860 G01 Load Step Transient Response (2-Phase) ILOAD 10A/DIV IL1 5A/DIV IL2 5A/DIV VOUT 50mV/DIV VIN = 12V 50s/DIV VOUT = 1.8V ILOAD STEP = 10A 3860 G02 Load Step Transient Response (2-Phase) ILOAD 10A/DIV IL1 5A/DIV IL2 5A/DIV VOUT 50mV/DIV VIN = 12V 50s/DIV VOUT = 1.2V ILOAD STEP = 10A 3860 G03 3860f LTC3860 Typical perFormance characTerisTics Load Step Transient Response (2-Phase with 50% Inductor Mismatch) VOUT(AC) 100mV/DIV ILOAD 20A/DIV IL1 = 320nH 10A/DIV IL2 = 220nH 10A/DIV 50s/DIV VIN = 12V VOUT = 1.2V ILOAD = 0A TO 25A 3860 G05 Efficiency and Power Loss vs Load Current 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 LOAD CURRENT (A) 10 3 2 1 0 100 3860 G06 VIN = 6V VOUT = 1.2V 7 6 5 4 POWER LOSS (W) Efficiency and Power Loss vs Supply Voltage 90 88 86 EFFICIENCY (%) 84 82 80 78 76 74 72 70 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) 13 VOUT = 1.2V IOUT = 15A 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 14 POWER LOSS (W) SW NODE 5V/DIV Short-Circuit Protection VOUT 1V/DIV VIN = 12V 10ms/DIV VOUT = 1.2V ILOAD = SHORTED 3860 G08 3860 G07 Regulated VFB vs Supply Voltage 0.604 OSCILLATOR FREQUENCY (MHz) 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 Oscillator Frequency vs RFREQ 610 OSCILLATOR FREQUENCY (kHz) 605 600 595 590 585 580 Oscillator Frequency vs Temperature 0.602 REGULATED VFB (V) 0.600 0.598 0.596 3 4 5 SUPPLY VOLTAGE (V) 6 3860 G10 0 20 40 80 60 RFREQ (k ) 100 120 3860 G11 575 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3860 G12 3860f LTC3860 Typical perFormance characTerisTics Oscillator Frequency vs Supply Voltage 1.300 OSCILLATOR FREQUENCY (MHz) 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 3.0 3.5 4.0 5.0 4.5 SUPPLY VOLTAGE (V) 5.5 3860 G13 Soft-Start Start-Up VOUT1 200mV/DIV VIN = 12V 5ms/DIV VOUT1 = 1.2V 0.1F CAPACITOR ON TRACK/SS1 3860 G15 Raitometric Tracking Start-Up TRACK/SS1 500mV/DIV Coincident Tracking Start-Up TRACK/SS1 500mV/DIV VOUT1 500mV/DIV VOUT1 500mV/DIV 2s/DIV CHANNEL 1 TRACKING OFF PULSE GENERATOR 3860 G16 2s/DIV CHANNEL 1 TRACKING OFF PULSE GENERATOR 3860 G17 Line Step Transient Response (2-Phase) VOUT 50mV/DIV IL1 5A/DIV IL2 5A/DIV VIN 5V/DIV COMP1 100mV/DIV VIN = 12V 20s/DIV VOUT = 1.8V VIN STEP = 7V TO 14V 3860 G18 Line Step Transient Response (2-Phase) VOUT 50mV/DIV IL1 5A/DIV IL2 5A/DIV VIN 5V/DIV COMP1 100mV/DIV VIN = 12V 20s/DIV VOUT = 1.2V VIN STEP = 7V TO 14V 3860 G19 Line Step Transient Response (Single Phase) VOUT 50mV/DIV IL 2A/DIV VIN 5V/DIV COMP1 100mV/DIV 20s/DIV VOUT = 1.2V VIN STEP = 7V TO 14V 3860 G20 3860f LTC3860 pin FuncTions VCC (Pin 1): Chip Supply Voltage. Bypass this pin to GND with a capacitor (0.1F to 1F ceramic) in close proximity to the chip. FB1 (Pin 2), FB2 (Pin 8): Error Amplifier Inverting Inputs. FB1 or FB2 can be connected to VSNSOUT via a resistor divider for remote VOUT sensing. The bottom of the divider should be connected to the SGND pin of the IC. The other FB, when used, is typically connected to the other VOUT via a resistor divider, also terminated at the IC SGND pin. COMP1 (Pin 3), COMP2 (Pin 7): Error Amplifier Outputs. PWM duty cycle increases with this control voltage. The error amplifiers in the LTC3860 are true operational amplifiers with low output impedance. As a result, the outputs of two active error amplifiers cannot be directly connected together! For multiphase operation, connecting the FB pin on an error amplifier to VCC will three-state the output of that amplifier. Multiphase operation can then be achieved by connecting all of the COMP pins together and using one channel as the master and all others as slaves. VSNSOUT (Pin 4): Differential Amplifier Output. VSNSN (Pin 5): Remote Sense Differential Amplifier Inverting Input. Connect this pin to sense ground at the output load. VSNSP (Pin 6): Remote Sense Differential Amplifier Noninverting Input. Connect this pin to VOUT at the output load. FREQ (Pin 10): Frequency Set/Select Pin. If CLKIN is high, the resistor between this pin and SGND sets the switching frequency. If CLKIN is low, the logic state of this pin sets frequency. This pin sources 20A. CLKIN (Pin 11): External Clock Synchronization Input Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. Otherwise, if high, a resistor from FREQ to SGND sets frequency; if low, FREQ state sets frequency. CLKOUT (Pin 12): Clock Output Pin. Used to synchronize other LTC3860s. PHSMD (Pin 13): Phase Mode Pin. Selects Ch1-Ch2 and Ch1-CLKOUT phase relationship. ISNS1N (Pin 21), ISNS2N (Pin 20): Current Sense Amplifier (-) Input. The (-) input to the current amplifier is normally connected to the respective VOUT. ISNS1P (Pin 22), ISNS2P (Pin 19): Current Sense Amplifier (+) Input. The (+) input to the current sense amplifier is normally connected to the midpoint of the inductor's parallel RC sense circuit or to the node between the inductor and sense resistor if using a discrete sense resistor. ILIM1 (Pin 23), ILIM2 (Pin 18): Current Comparator Sense Voltage Limit Selection Pin. Connect a resistor from this pin to SGND. This pin sources 20A. The resultant voltage sets the threshold for overcurrent protection. RUN1 (Pin 24), RUN2 (Pin 17): Run Control Inputs. A voltage above 2.25V on either pin turns on the IC. However, forcing either of these pins below 2V causes the IC to shut down that particular channel. There are 1.5A pull-up currents for these pins. PWM1 (Pin 25), PWM2 (Pin 16): (Top) Gate Signal Output. This signal goes to the PWM or top gate input of the external gate driver or integrated driver MOSFET. This is a three-state compatible output. 3860f LTC3860 pin FuncTions PWMEN1/PWMEN2 (Pin 26/Pin 15): Enable Pin for NonThree-State compatible drivers. This pin has an internal open-drain pull-up to VCC. An external resistor to SGND is required. This pin is low when the corresponding PWM pin is high impedance. PGOOD1 (Pin 27), PGOOD2 (Pin 14): Power Good Pins. Open-drain outputs that pull to ground when output voltage is not in regulation. IAVG (Pin 28): Average Current Output Pin. A capacitor tied to ground from this pin stores a voltage proportional to the average per-phase current when multiple outputs are tied together. Each phase contributes information to this average through internal resistors when in current sharing mode. SGND (Pins 29, 30, Exposed Pad Pin 33): Ground. Pins 29, 30 and 33 are electrically connected internally. It is recommended that the exposed pad be soldered to the PCB. VINSNS (Pin 31): VIN Sense Pin. Connects to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and changes the pulse width in an inversely proportional manner, thus bypassing the feedback loop and providing excellent transient line regulation. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. TRACK/SS1 (Pin 32), TRACK/SS2 (Pin 9): Soft-Start. The voltage ramp rate at these pins sets the voltage ramp rate of the outputs. Self soft-start is accomplished by placing a capacitor to ground. 3860f LTC3860 FuncTional Diagram 1 4 6 VSNSOUT VSNSP DA 100k VCC 29 SGND 30 SGND VCC 24 RUN1 100k 1.5A VSNSN VCC 1.5A BG/BIAS 3 COMP1 REF TRACK/SS1 FB1 VCC SD/UVLO PGOOD 17 RUN2 27 PGOOD1 14 PGOOD2 5 VFB1 VFB2 + + - NOC1 EA1 32 2 + OC1 OC2 OV1 OV2 PWM1 PWMEN1 25 26 16 15 9 8 7 REF TRACK/SS2 FB2 COMP2 + + - VFB1 ILIM1 VFB2 ILIM2 MASTER/SLAVE/ INDEPENDENT? EA2 LOGIC + NOC2 PWM2 PWMEN2 RAMP/SLOPE/ FEEDFORWARD VCC 20A VINSNS 31 S 22 ISNS1P + x18.5 21 ISNS1N - S VCC 20A OC1 NOC1 19 ISNS2P + x18.5 VCC 20A OC2 NOC2 IAVG 28 ILIM2 18 ILIM1 23 PLL/VCO FREQ PHSMD CLKOUT CLKIN 10 13 12 11 3860 BD 20 ISNS2N - 3860f LTC3860 operaTion (Refer to Functional Diagram) Main Control Architecture The LTC3860 is a dual-channel/dual-phase, constant frequency, voltage mode controller for DC/DC step-down applications. It is designed to be used in a synchronous switching architecture with external integrated-driver MOSFETs or external drivers and N-channel MOSFETs using single wire three-state PWM interfaces. The controller allows the use of sense resistors or lossless inductor DCR current sensing to maintain current balance between phases and to provide overcurrent protection. The operating frequency is selectable from 250kHz to 1.25MHz. To mulitply the effective switching frequency, multiphase operation can be extended to 3, 4, 6, or 12 phases by paralleling up to 6 controllers. In single or 3-phase operation, the 2nd or 4th channel can be used as an independent output. The output of the differential amplifier is connected to the error amplifier inverting input (FB) through a resistor divider. The remote sense differential amplifier output (VSNSOUT) provides a signal equal to the differential voltage (VSNSP - VSNSN) sensed across the output capacitor, but re-referenced to the local ground (SGND). This permits accurate voltage sensing at the load, without regard to the potential difference between its ground and local ground. In the main voltage mode control loop, the error amplifier output (COMP) directly controls the converter duty cycle in order to drive the FB pin to 0.6V in steady state. Dynamic changes in output load current can perturb the output voltage. When the output is below regulation, COMP rises, increasing the duty cycle. If the output rises above regulation, COMP will decrease, decreasing the duty cycle. As the output approaches regulation, COMP will settle to the steady-state value representing the stepdown conversion ratio. In normal operation, the PWM latch is set high at the beginning of the clock cycle (assuming COMP > 0.5V). When the (line feedforward compensated) PWM ramp exceeds the COMP voltage, the comparator trips and resets the PWM latch. If COMP is less than 0.5V at the beginning of the clock cycle, as in the case of an overvoltage at the outputs, the PWM pin remains low throughout the entire cycle. When the PWM pin goes high it has a minimum on-time of approximately 20ns and a minimum off-time of approximately 1/12th the switching period. Current Sharing In multiphase operation, the LTC3860 also incorporates an auxiliary current sharing loop. Inductor current is sampled each cycle. Each phase's current sense amplifier output is averaged at the IAVG pin. A small capacitor connected from IAVG to GND (typically 100pF) stores a voltage corresponding to the instantaneous average current of all phases. Each phase integrates the difference between its current and the average. Within each phase the integrator output is proportionally summed with the system error amplifier voltage (COMP), adjusting that phase's duty cycle to equalize the currents. When multiple ICs are daisy-chained the IAVG pins must be connected together. When the phases are operated independently, the IAVG pin should be tied to ground. Figure 1 shows a transient load step with 50% inductor mismatch in a 2-phase system. VOUT(AC) 100mV/DIV ILOAD 20A/DIV IL1 = 320nH 10A/DIV IL2 = 220nH 10A/DIV 50s/DIV VIN = 12V VOUT = 1.2V ILOAD = 0A TO 25A 3860 G05 Figure 1 3860f 0 LTC3860 operaTion (Refer to Functional Diagram) Overcurrent Protection The current sense amplifier outputs also connect to overcurrent (OC) comparators that provide fault protection in the case of an output short. When an OC fault is detected, the controller three-states the PWM output, resets the soft-start capacitor, and waits for 32768 clock cycles before attempting to start up again. The LTC3860 also provides negative OC (NOC) protection by preventing turn-on of the bottom MOSFET during a negative OC fault condition. The negative OC threshold is equal to -3/4 the positive OC threshold. See Applications Information for guidelines on setting these thresholds. Excellent Transient Response The LTC3860 error amplifiers are true operational amplifiers, meaning that they have high bandwidth, high DC gain, low offset and low output impedance. Their bandwidth, when combined with high switching frequencies and lowvalue inductors, allows the compensation network to be optimized for very high control loop crossover frequencies and excellent transient response. The 600mV internal reference allows regulated output voltages as low as 600mV without external level-shifting amplifiers. Line Feedforward Compensation The LTC3860 achieves outstanding line transient response using a feedforward correction scheme which instantaneously adjusts the duty cycle to compensate for changes in input voltage, significantly reducing output overshoot and undershoot. It has the added advantage of making the DC loop gain independent of input voltage. Figure 2 shows how large transient steps at the input have little effect on the output voltage. VOUT 50mV/DIV IL 2A/DIV VIN 5V/DIV COMP1 100mV/DIV 20s/DIV VOUT = 1.2V VIN STEP = 7V TO 14V 3860 G20 Figure 2 Remote Sense Differential Amplifier The LTC3860 includes a low offset, unity gain, high bandwidth differential amplifier for remote output sensing. Output voltage accuracy is significantly improved by removing board interconnection losses from the total error budget. The LTC3860 differential amplifier has a typical output slew rate of 45V/s, bandwidth of 20MHz, input referred offset < 2mV and a typical maximum output voltage of VCC - 1V. The amplifier is configured for unity gain, meaning that the differential voltage between VSNSP and VSNSN is translated to VSNSOUT, relative to SGND. 3860f LTC3860 operaTion (Refer to Functional Diagram) Shutdown Control Using the RUN Pins The two channels of the LTC3860 can be independently enabled using the RUN1 and RUN2 pins. When both pins are driven low all internal circuitry, including the internal reference and oscillator, are completely shut down. A 1.5A pull-up current is provided for each RUN pin internally. The RUN pins remain low impedance up to VCC. From VCC to 6V, they may sink some current. Undervoltage Lockout To prevent operation of the power supply below safe input voltage levels, both channels are disabled when VCC is below the undervoltage lockout (UVLO) threshold (2.9V falling, 3V rising). If a RUN pin is driven high, the LTC3860 will start up the reference to detect when VCC rises above the UVLO threshold, and enable the appropriate channel. Overvoltage Protection If the output voltage rises to more than 10% above the set regulation value, which is reflected as a VFB voltage of 0.66V or above, the LTC3860 will force the PWM output low to turn on the bottom MOSFET and discharge the output. Normal operation resumes once the output is back within the regulation window. However, if the reverse current flowing from VOUT back through the bottom power MOSFET to PGND is greater than 3/4 the positive OC threshold, the NOC comparator trips and shuts off the bottom power MOSFET to protect it from being destroyed. This scenario can happen when the LTC3860 tries to start into a precharged load, higher than the OV threshold. As a result, the bottom switch turns on until the amount of reverse current trips the NOC comparator threshold. Internal Soft-Start By default, the start-up of each channel's output voltage is normally controlled by an internal soft-start ramp. The internal soft-start ramp represents a noninverting input to the error amplifier. The FB pin is regulated to the lower of the error amplifier's three noninverting inputs (the internal soft-start ramp for that channel, the TRACK/SS pin or the internal 600mV reference). As the ramp voltage rises from 0V to 0.6V over approximately 2ms, the output voltage rises smoothly from its pre-biased value to its final set value. Certain applications can result in the start-up of the converter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the bottom MOSFET is disabled until soft-start is complete. However, the bottom MOSFET will be turned on for 20ns every 8 cycles to allow the driver IC to recharge its topside gate drive capacitor. Soft-Start and Tracking Using TRACK/SS Pin The user can connect an external capacitor greater than 10nF to the TRACK/SS pin for the relevant channel to increase the soft-start ramp time beyond the internally set default. The TRACK/SS pin represents a noninverting input to the error amplifier and behaves identically to the internal ramp described in the previous section. An internal 2.5A current source charges the capacitor, creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS pin voltage rises from 0V to 0.6V, the output voltage rises smoothly from 0V to its final value in: CSS * 0.6 V seconds . 2.5A 3860f LTC3860 operaTion (Refer to Functional Diagram) Alternatively, the TRACK/SS pin can be used to force the start-up of VOUT to track the voltage of another supply. Typically this requires connecting the TRACK/SS pin to an external divider from the other supply to ground (see Applications Information). It is only possible to track another supply that is slower than the internal soft-start ramp. The TRACK/SS pin also has an internal open-drain NMOS pull-down transistor that turns on to reset the TRACK/SS voltage when the channel is shut down (RUN = 0V or VCC < UVLO threshold) or during an OC fault condition. In multiphase operation, one master error amplifier is used to control all of the PWM comparators. The FB pins for the unused error amplifiers are connected to VCC in order to three-state these amplifier outputs, and the COMP pins are connected together. The TRACK/SS pins should also be connected together so that the slave phases can detect when soft-start is complete and enable the bottom MOSFET. Frequency Selection and the Phase-Locked Loop (PLL) The selection of the switching frequency is a tradeoff between efficiency, transient response and component size. High frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. However, efficiency is generally lower due to increased transition and switching losses. The LTC3860's switching frequency can be set in three ways: using an external resistor to linearly program the frequency, synchronizing to an external clock, or simply selecting one of two fixed frequencies (400kHz and 600kHz). Table 1 highlights these modes. Table 1. Frequency Selection CLKIN PIN Clocked High Low Low FREQ PIN RFREQ to GND RFREQ to GND Low High FREQUENCY 250kHz to 1.25MHz 250kHz to 1.25MHz 400kHz 600kHz No external PLL filter is required to synchronize the LTC3860 to an external clock. Applying an external clock signal to the CLKIN pin will automatically enable the PLL with internal filter. Constant frequency operation brings with it a number of benefits: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly specified. Noise generated by the circuit will always be at known frequencies. Subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC3860. Using the CLKOUT and PHSMD Pins in Multiphase Applications The LTC3860 features CLKOUT and PHSMD pins that allow multiple LTC3860 ICs to be daisy-chained together in multiphase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional ICs in a 3-, 4-, 6- or 12-phase power supply solution feeding a single high current output, or even several outputs from the same input supply. The PHSMD pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and CLKOUT, as summarized in Table 2. The phases are calculated relative to zero degrees, defined as the rising edge of PWM1. Refer to Applications Information for more details on how to create multiphase applications. Table 2. Phase Selection PHSMD PIN Float Low High CH-1 to CH-2 PHASE 180 180 120 CH-1 to CLKOUT PHASE 90 60 240 3860f LTC3860 operaTion (Refer to Functional Diagram) Using the LTC3860 Error Amplifiers in Multiphase Applications Due to the low output impedance of the error amplifiers, multiphase applications using the LTC3860 use one error amplifier as the master with all of the slaves' error amplifiers disabled. The channel 1 error amplifier (phase = 0) may be used as the master with phases 2 through n (up to 12) serving as slaves. To disable the slave error amplifiers connect the FB pins of the slaves to VCC. This three-states the output stages of the amplifiers. All COMP pins should then be connected together to create PWM outputs for all phases. As noted in the section on soft-start, all TRACK/SS pins should also be shorted together. Refer to the Multiphase Operation section in Applications Information for schematics of various multiphase configurations. Theory and Benefits of Multiphase Operation Multiphase operation provides several benefits over traditional single phase power supplies: n n n n bandwidth to approximately n/3-times the actual switching frequency. This improves transient response, as well as reducing component size and increasing real world operating efficiency. Power Good Indicator Pins (PGOOD1, PGOOD2) Each PGOOD pin is connected to the open drain of an internal pull-down device which pulls the PGOOD pin low when the corresponding FB pin voltage is outside the PGOOD regulation window (7.5% entering regulation, 10% leaving regulation). The PGOOD pins are also pulled low when the corresponding RUN pin is low, or during UVLO. In multiphase applications, one FB pin and error amplifier are used to control all of the phases. PGOOD outputs for the slave phases may be left unconnected as they will not report fault conditions. PWM and PWMEN Pins The PWM pins are three-state compatible outputs, designed to drive MOSFET drivers, DRMOSs, etc which do not represent a heavy capacitive load. An external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. The PWMEN outputs have an open-drain pull-up to VCC and require an appropriate external pull-down resistor. This pin is intended to drive the enable pins of the MOSFET drivers that do not have three-state compatible PWM inputs. PWMEN is low only when PWM is high impedance, and high at any other PWM state. Greater output current capability Improved transient response Reduction in component size Increased real world operating efficiency Because multiphase operation parallels power stages, the amount of output current available is n times what it would be with a single comparable output stage, where n is equal to the number of phases. Interleaving of multiple power stages increases the effective switching frequency that the control loop sees, correspondingly increasing the practical control loop 3860f LTC3860 applicaTions inFormaTion Setting the Output Voltage The LTC3860 regulates the FB pins to 0.6V. FB is connected to VOUT or VSNSOUT (for remote output sensing) via an external resistive divider as shown in Figure 3. The divider sets the output voltage according to the following equation: R VOUT = 0.6 V * 1+ B RA Care should be taken to place the output divider resistors and the compensation components as close as possible to the FB pin to minimize switching noise coupling into the control signal path. COMP LTC3860 VOUT FB RA SGND 3860 F03 Programming the Operating Frequency The LTC3860 can be hard wired to one of two fixed frequencies, linearly programmed to any frequency between 250kHz and 1.25MHz or synchronized to an external clock. Table 1 in the Operation section shows how to connect the CLKIN and FREQ pins to choose the mode of frequency programming. In linear programming mode the frequency of operation is given by the following equation: Frequency (RFREQ - 15k ) * 20Hz/ Figure 4 shows operating frequency vs RFREQ. 1.7 OSCILLATOR FREQUENCY (MHz) 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0.1 0 20 40 80 60 RFREQ (k ) 100 120 3860 G11 RB COUT DIVIDER AND COMPENSATION COMPONENTS PLACED NEAR FB, SGND AND COMP PINS Figure 3. Output Divider and Compensation Component Placement Figure 4. Operating Frequency vs RFREQ Sensing the Output Voltage with a Differential Amplifier When using the remote sense differential amplifier, care should be taken to route the VSNSP and VSNSN PCB traces parallel to each other all the way to the terminals of the output capacitor or remote sensing points on the board. In addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. Ideally, they should be shielded by a low impedance ground plane to maintain signal integrity. When using a single LTC3860 to regulate two output voltages, the negative terminal of VOUT2 should be kelvin-connected to SGND and the differential amplifier should be used to remotely sense VOUT1. This will maximize output voltage accuracy for both channels. Frequency Synchronization The LTC3860 incorporates an internal phase-locked loop (PLL) which enables synchronization of the internal oscillator (rising edge of PWM1) to an external clock from 250kHz to 1.25MHz. Since the entire PLL is internal to the LTC3860, simply applying a CMOS level clock signal to the CLKIN pin will enable frequency synchronization. A resistor from FREQ to GND is still required to set the free running frequency close to the sync input frequency. Choosing the Inductor and Setting the Current Limit The inductor value is related to the switching frequency, which is chosen based on the tradeoffs discussed in the 3860f LTC3860 applicaTions inFormaTion Operation section. The inductor can be sized using the following equation: V L = OUT f * IL V * 1- OUT VIN a voltage corresponding to the current limit. The current sense circuit has a voltage gain of 20 and a zero current level of 500mV. Therefore, the current limit resistor should be set using the following equation: RILIM = 18.5 * ILIMIT(SET ) * RSENSE + 0.55V 20A Choosing a larger value of IL leads to smaller L, but results in greater core loss (and higher output voltage ripple for a given output capacitance and/or ESR). A reasonable starting point for setting the ripple current is 30% of the maximum output current, or: IL = 0.3 * IOUT The inductor saturation current rating needs to be higher than the peak inductor current during transient conditions. If IOUT is the maximum rated load current, then the maximum transient current, IMAX, would normally be chosen to be some factor (e.g., 60%) greater than IOUT: IMAX = 1.6 * IOUT The minimum saturation current rating should be set to allow margin due to manufacturing and temperature variation in the sense resistor or inductor DCR. A reasonable value would be: ISAT = 2.2 * IOUT The programmed current limit must be low enough to ensure that the inductor never saturates and high enough to allow increased current during transient conditions and allow margin for DCR variation. For example, if: ISAT = 2.2 * IOUT and IMAX = 1.6 * IOUT A reasonable ILIMIT would be: ILIMIT = 2 * IOUT If the sensed inductor current exceeds current limit, the IC will three-state the PWM outputs, reset the soft-start timer and wait 32768 switching cycles before attempting to return the output to regulation. The current limit is programmed using a resistor from the ILIM pin to SGND. The ILIM pin sources 20A to generate In multiphase applications only one current limit resistor should be used per LTC3860. The ILIM2 pin should be tied to VCC. Internal logic will then cause channel 2 to use the same current limit levels as channel 1. If an LTC3860 has a slave and an independent, then both ILIM pins must be independently set to the right voltage. Inductor Core Selection Once the value of L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core losses found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Also, core losses decrease as inductance increases. Unfortunately, increased inductance requires more turns of wire, larger inductance and larger copper losses. Ferrite designs have very low core loss and are preferred at high switching frequencies. However, these core materials exhibit "hard" saturation, causing an abrupt reduction in the inductance when the peak current capability is exceeded. Do not allow the core to saturate! CIN Selection The input bypass capacitor in an LTC3860 circuit is common to both channels. The input bypass capacitor needs to meet these conditions: its ESR must be low enough to keep the supply drop low as the top MOSFETs turn on, its RMS current capability must be adequate to withstand the ripple current at the input, and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor (particularly a non-ceramic type) that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. The input capacitor's voltage rating should be at least 1.4 times the maximum input voltage. Power loss due to ESR 3860f LTC3860 applicaTions inFormaTion occurs not only as I2R dissipation in the capacitor itself, but also in overall battery efficiency. For mobile applications, the input capacitors should store adequate charge to keep the peak battery current within the manufacturer's specifications. The input capacitor RMS current requirement is simplified by the multiphase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worstcase RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used to determine the maximum RMS current requirement. Increasing the output current drawn from the other out-of-phase controller will actually decrease the input RMS ripple current from this maximum value. The out-of-phase technique typically reduces the input capacitor's RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top N-channel MOSFET is approximately a square wave of duty cycle VOUT/VIN. The maximum RMS capacitor current is given by: IRMS IOUT(MAX ) VOUT ( VIN - VOUT ) VIN Ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics' higher ESR and dryout possibility require several to be used. Sanyo , OS-CON SVP SVPD series; Sanyo POSCAP TQC series or aluminum electrolytic capacitors from Panasonic WA series or Cornel Dublilier SPV series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low ESR and high bulk capacitance. COUT Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple VOUT is approximately bounded by: 1 VOUT IL ESR + 8 * fSW * COUT where IL is the inductor ripple current. IL may be calculated using the equation: IL = VOUT VOUT 1- L * fSW VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The total RMS current is lower when both controllers are operating due to the interleaving of current pulses through the input capacitors. This is why the input capacitance requirement calculated above for the worst-case controller is adequate for the dual controller design. Note that capacitor manufacturer's ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Since IL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Sanyo, Panasonic and Cornell Dublilier should be considered for high performance through-hole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to offset the effect of lead inductance. 3860f LTC3860 applicaTions inFormaTion In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or transient current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent output capacitor choices include the Sanyo POSCAP TPD, TPE, TPF series, the Kemet T520, T530 and A700 series, NEC/Tokin NeoCapacitors and Panasonic SP series. Other capacitor types include Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. Current Sensing To maximize efficiency the LTC3860 is designed to sense current through the inductor's DCR, as shown in Figure 6. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which for most inductors applicable to this application, is between 0.3 and 1m. If the filter RC time constant is chosen to be exactly equal to the L/DCR time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR. Check the manufacturer's data sheet for specifications regarding the inductor DCR in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. Since the temperature coefficient of the inductor's DCR is 3900ppm/C, first order compensation of the filter time constant is possible by using filter resistors with an equal but opposite (negative) TC, assuming a low TC capacitor is used. That is, as the inductor's DCR rises with increasing temperature, the L/DCR time constant drops. Since we want the filter RC time constant to match the L/DCR time constant, we also want the filter RC time constant to drop with increasing temperature. Typically, the inductance will also have a small negative TC. The ISNSP and ISNSN pins are the inputs to the current comparators. The common mode range of the current comparators is -0.3V to VCC + 0.1V. Continuous linear operation is provided throughout this range, allowing output voltages between 0.6V (the reference input to the error amplifiers) and VCC + 0.1V. The maximum differential current sense input (VISNSP - VISNSN) is 50mV. The high impedance inputs to the current comparators allow accurate DCR sensing. However, care must be taken not to float these pins during normal operation. Filter components mutual to the sense lines should be placed close to the LTC3860, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 5). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If low value (<5m) sense resistors are used, verify that the signal across CF resembles the current through the inductor, and reduce RF to eliminate any large step associated with the turn-on of the primary switch. If DCR sensing is used (Figure 6b), sense resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. The capacitor C1 should be placed close to the IC pins. TO SENSE FILTER, NEXT TO THE CONTROLLER COUT INDUCTOR OR RSENSE 3860 F05 Figure 5. Sense Lines Placement with Inductor or Sense Resistor 3860f LTC3860 applicaTions inFormaTion VINSNS 5V VCC LTC3860 PWM GND ISNSN ISNSP CF VLOGIC BOOST TG VCC LTC4449 TS IN GND RF RF FILTER COMPONENTS PLACED NEAR SENSE PINS BG VIN 12V SENSE RESISTOR PLUS PARASITIC INDUCTANCE L RS ESL VOUT CF * 2RF ESL/RS POLE-ZERO CANCELLATION 3860 F06a (6a) Using a Resistor to Sense Current VINSNS 5V VCC LTC3860 PWM GND ISNSN ISNSP C1* VLOGIC BOOST TG VCC LTC4449 IN TS GND BG R1* INDUCTOR L DCR VOUT VIN 12V 3860 F06b R1 * C1 = L *PLACE R1 NEAR INDUCTOR DCR PLACE C1 NEAR ISNSP ISNSN PINS , (6b) Using the Inductor to Sense Current Figure 6. Two Different Methods of Sensing Current Multiphase Operation When the LTC3860 is used in a single output, multiphase application the slave error amplifiers must be disabled by connecting their FB pins to VCC. All current limits should be set to the same value using only one resistor to SGND per IC. ILIM2 should then be connected to VCC. These connections are shown in Table 3. In a multiphase application all COMP RUN and TRACK/SS pins must be , connected together. Table 3. Multiphase Configurations CH1 Master Slave Slave FB2 Off (FB = VCC) Slave Off Off (FB = VCC) (FB = VCC) Additional Off On Output (FB = VCC) CH2 Slave FB1 On ILIM1 Resistor to GND Resistor to GND Resistor to GND ILIM2 VCC VCC Resistor to GND For output loads that demand high current, multiple LTC3860s can be cascaded to run out of phase to provide more output current without increasing input and output voltage ripple. The CLKIN pin allows the LTC3860 to synchronize to the CLKOUT signal of another LTC3860. The CLKOUT signal can be connected to the CLKIN pin of the following LTC3860 stage to line up both the frequency and the phase of the entire system. Tying the PHSMD pin to VCC, SGND or floating it generates a phase difference (between CLKIN and CLKOUT) of 240, 60 or 90 respectively, and a phase difference (between CH1 and CH2) of 120, 180 or 180. Figure 7 shows the PHSMD connections necessary for 3-, 4-, 6- or 12-phase operation. A total of 12 phases can be cascaded to run simultaneously out of phase with respect to each other. 3860f LTC3860 applicaTions inFormaTion VSNSOUT2 VSNSOUT1 VCC 0, 120 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +240 VCC 240, 60 CLKIN CLKOUT PHSMD TRACK/SS2 FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1 3960 F07a VSNSOUT1 VCC 0, 180 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +90 VCC 90, 270 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 3960 F07b Figure 7a. 3-Phase Operation VSNSOUT1 VCC VCC VCC Figure 7b. 4-Phase Operation 0, 180 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 60, 240 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 120, 300 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 3960 F07c Figure 7c. 6-Phase Operation VSNSOUT1 VCC VCC VCC 0, 180 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 60, 240 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 120, 300 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +90 VCC 210, 30 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 VCC 270, 90 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 +60 VCC 330, 150 CLKIN CLKOUT PHSMD FB1 FB2 LTC3860 ILIM2 COMP1 ILIM1 COMP2 IAVG TRACK/SS1,2 3960 F07d Figure 7d. 12-Phase Operation 3860f 0 LTC3860 applicaTions inFormaTion A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. Figure 8 graphically illustrates the principle. The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst case RMS ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the current in each stage is balanced. Refer to Application Note 19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figures 9 and 10 illustrate how the input and output currents are reduced by using an additional phase. For a 2-phase converter, the input current peaks drop in half and the frequency is doubled. The input capacitor requirement is thus reduced theoretically by a factor of four! Just imagine the possibility of capacitor savings with even higher number of phases! SINGLE PHASE SW1 V ICIN ICOUT IL2 ICIN ICOUT RIPPLE 3860 F08 1.0 0.9 0.8 0.7 DIC(P-P) VO/L 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 2 PHASE 1 PHASE 3860 F09 Figure 9. Normalized Output Ripple Current vs Duty Factor [IRMS 0.3 (DIC(PP))] 0.6 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.5 0.4 0.3 0.2 0.1 0 2 PHASE 1 PHASE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 DUAL PHASE SW1 V SW2 V IL1 3860 F10 Figure 10. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages Output Current Sharing When multiple LTC3860s are cascaded to drive a common load, accurate output current sharing is essential to achieve optimal performance and efficiency. Otherwise, if one stage is delivering more current than another, then the temperature between the two stages will be different, and that could translate into higher switch RDS(ON), lower efficiency, and higher RMS ripple. When the COMP and IAVG pins of multiple LTC3860s are tied together, the amount of output current delivered from each LTC3860 is actively balanced by the IAVE loop. The SGND pins of the multiple LTC3860s must be kelvined to the same point for optimal current sharing. 3860f Figure 8. Single and 2-Phase Current Waveforms LTC3860 applicaTions inFormaTion Dual-Channel Operation The LTC3860 can control two independent power supply outputs with no channel-to-channel interaction or jitter. The following recommendations will ensure maximum performance in this mode of operation: n Tracking and Soft-Start (TRACK/SS Pins) The start-up of the supply output is controlled by the voltage on the TRACK/SS pin for that channel. The LTC3860 regulates the FB pin voltage to the lower of the voltage on the TRACK/SS pin and the internal 600mV reference. The TRACK/SS pin can therefore be used to program an external soft-start function or allow the output supply to track another supply during start-up. External soft-start is enabled by connecting a capacitor from the TRACK/SS pin to SGND. An internal 2.5A current source charges the capacitor, creating a linear voltage ramp at the TRACK/SS pin, and causing the output supply to rise smoothly from its pre-biased value to its final regulated value. The total soft-start time is approximately: t SS = CSS * 600mV 2.5A The output of channel 1 should be sensed using the remote sense differential amplifier. The SGND pins and exposed pad and all local small-signal GND should then be a Kelvin connection to the negative terminal of the channel 2 output. This will provide the best possible regulation on channel 2 without adversely affecting channel 1. Due to internal logic used to determine the mode of operation, separate current limit resistors should be used for each channel in dual-channel operation, even when the values are the same. n Table 4 shows the ILIM and EA configuration for dualchannel operation. Table 4. Dual-Channel Configuration CH1 CH2 Independent Independent EA1 On EA2 On ILIM1 Resistor to GND ILIM2 Resistor to GND VOUT1 R1B R1A RTRACKB Alternatively, the TRACK/SS pin can be used to track another supply during start-up. For example, Figure 11a shows the start-up of VOUT2 controlled by the voltage on the TRACK/SS2 pin. Normally this pin is used to allow the start-up of VOUT2 to track that of VOUT2 LTC3860 FB1 FB2 R2A R2B TRACK/SS2 RTRACKA 3860 F11a Figure 11a. Using the TRACK/SS Pin VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1 VOUT2 VOUT2 TIME TIME 3860 F11b_c (11b) Coincident Tracking (11c) Ratiometric Tracking 3860f Figure 11b and 11c. Two Different Modes of Output Voltage Tracking LTC3860 applicaTions inFormaTion VOUT1 as shown qualitatively in Figures 11a and 11b. When the voltage on the TRACK/SS2 pin is less than the internal 0.6V reference, the LTC3860 regulates the FB2 voltage to the TRACK/SS2 pin voltage instead of 0.6V. The start-up of VOUT2 may ratiometrically track that of VOUT1, according to a ratio set by a resistor divider (Figure 11c): VOUT1 R + R TRACKB R2A = * TRACKA VOUT 2 R TRACKA R2B + R2A For coincident tracking (VOUT1 = VOUT2 during start-up), R2A = RTRACKA R2B = RTRACKB The ramp time for VOUT2 to rise from 0V to its final value is: t SS2 = t SS1 * 0.6 VOUT1F VOUT2F VOUT1F * R TRACKA + R TRACKB R TRACKA C3 R1 RB VREF R3 FB R2 C1 GAIN (dB) VOUT C2 PHASE (DEG) -1 GAIN +1 -1 0 COMP FREQ -90 -180 Figure 12. Type 3 Amplfier Compensation The positive input of the error amplifier is connected to an internal 600mV reference, while the negative input is connected to the FB pin. The output is connected to COMP , which is in turn connected to the line feedforward circuit and from there to the PWM generator. To speed up the overshoot recovery time, the maximum potential at the COMP pin is internally clamped. Unlike many regulators that use a transconductance (gm) amplifier, the LTC3860 is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows the feedback gain to be tightly controlled by external components, which is not possible with a simple gm amplifier. In addition, the voltage feedback amplifier allows flexibility in choosing pole and zero locations. In particular, it allows the use of "Type 3" compensation, which provides a phase boost at the LC pole frequency and significantly improves the control loop phase margin. In a typical LTC3860 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. All these components affect loop behavior and need to be accounted for in the loop compensation. The modulator consists of the PWM generator, the output MOSFET drivers and the external MOSFETs themselves. The modulator gain varies linearily with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. From a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input. It has fairly benign AC 3860f For coincident tracking, t SS2 = t SS1 * where VOUT1F and VOUT2F are the final, regulated values of VOUT1 and VOUT2. VOUT1 should always be greater than VOUT2 when using the TRACK/SS2 pin for tracking. If no tracking function is desired, then the TRACK/SS2 pin may be tied to a capacitor to ground, which sets the ramp time to final regulated output voltage. It is only possible to track another supply that is slower than the internal soft-start ramp. At the completion of tracking, the TRACK/SS pin must be >620mV, so as not to affect regulation accuracy and to ensure the part is in CCM mode. Feedback Loop Compensation The LTC3860 is a voltage mode controller with a second dedicated current sharing loop to provide excellent phaseto-phase current sharing in multiphase applications. The current sharing loop is internally compensated. While Type II compensation for the voltage control loop may be adequate in some applications (such as with the use of high ESR bulk capacitors), Type III compensation, along with ceramic capacitors, is recommended for optimum transient response. Referring to Figure 12, the error amplifiers sense the output voltage at VOUT. + - PHASE BOOST -270 -380 3806 F12 LTC3860 applicaTions inFormaTion behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency. The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a second order LC roll-off at the output with 180 phase shift. This roll-off is what filters the PWM waveform, resulting in the desired DC output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor will approach its ESR, and the roll-off due to the capacitor will stop, leaving -20dB/decade and 90 of phase shift. Figure 12 shows a Type 3 amplifier. The transfer function of this amplifier is given by the following equation: - (1+ sC1R2)[1+ s(R1+ R3)C3] VCOMP = VOUT sR1(C1+ C2) 1+ s(C1//C2)R2 (1+ sC3R3) choose: fC = Crossover frequency = fZ1(ERR) = fLC = fSW 10 1 2R2C1 fC 1 fZ2(RES) = = 5 2 (R1+ R3) C3 fP1(ERR) = fESR = 1 2R2(C1// C2) 1 fP2(RES ) = 5fC = 2R3C3 Required error amplifier gain at frequency fC: A f f 40 log 1+ C - 20 log 1+ C - 20 log ( AMOD ) fLC fESR fLC fP2(RES) fP2(RES) - fZ 2(RES) + 1+ f 1+ f fZ2(RES) R2 C C 20 log * R1 f fLC fP2(RES) 1+ C + f 1+ f ESR fESR - fLC C 2 2 The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, fC. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at fC. However, in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. If conditional stability is a concern, move the error amplifier's zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation components value: fSW = Switching frequency fLC = 1 2 LCOUT 1 2 RESR COUT where AMOD is the modulator and line feedforward gain and is equal to: AMOD VIN(MAX ) * DCMAX VSAW 9V / V Once the value of resistor R1, poles and zeros location have been decided, the value of R2, C1, C2, R3 and C3 can be obtained from the above equations. Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet show typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. fESR = 3860f LTC3860 applicaTions inFormaTion Inductor The inductor in a typical LTC3860 circuit is chosen for a specific ripple current and saturation current. Given an input voltage range and an output voltage, the inductor value and operating frequency directly determine the ripple current. The inductor ripple current in the buck mode is: IL = VOUT VOUT 1- ( f)(L) VIN tance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. Selection criteria for the power MOSFETs include the onresistance RDS(ON), input capacitance, breakdown voltage and maximum output current. For maximum efficiency, on-resistance RDS(ON) and input capacitance should be minimized. Low RDS(ON) minimizes conduction losses and low input capacitance minimizes switching and transition losses. MOSFET input capacitance is a combination of several components but can be taken from the typical "gate charge" curve included on most data sheets (Figure 13). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain VIN VGS MILLER EFFECT a QIN CMILLER = (QB - QA)/VDS b VGS V Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Thus highest efficiency operation is obtained at low frequency with small ripple current. To achieve this however, requires a large inductor. A reasonable starting point is to choose a ripple current between 20% and 40% of IO(MAX). Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductor in buck mode should be chosen according to: L VOUT VOUT 1- f IL(MAX ) VIN(MAX ) Power MOSFET Selection The LTC3680 requires at least two external N-channel power MOSFETs per channel, one for the top (main) switch and one or more for the bottom (synchronous) switch. The number, type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs' on-resistance is normally less important for overall efficiency than its input capaci- + - +V DS - 3860 F12 Figure 13. Gate Charge Characteristic 3860f LTC3860 applicaTions inFormaTion voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: V Main Switch Duty Cycle = OUT VIN Synchronous Switch Duty Cycle = VIN - VOUT VIN values for range from 0.005/C to 0.01/C depending on the particular MOSFET used. Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. Suitable drivers such as the LTC4449 are capable of driving large gate capacitances without significantly slowing transition times. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5 or less) to reduce noise and EMI caused by the fast transitions MOSFET Driver Selection Gate driver ICs, DRMOSs and power blocks with an interface compatible with the LTC3860's three-state PWM outputs or the LTC3860's PWM/PWMEN outputs can be used. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the system produce losses, three main sources usually account for most of the losses in LTC3860 applications: 1) I2R losses, 2) topside MOSFET transition losses, 3) gate drive current. 1. I2R losses occur mainly in the DC resistances of the MOSFET, inductor, PCB routing, and input and output capacitor ESR. Since each MOSFET is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. Therefore in high step-down ratio applications the bottom MOSFET should have a much lower RDS(ON) than the top MOSFET. It is crucial that careful attention is paid to the layout of the power path on the PCB to minimize its resistance. In a 2-phase, 1.2V output, 60A system, 1m of PCB resistance at the output costs 5% in efficiency. 3860f The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: VOUT (IMAX )2 (1+ )RDS(ON) + VIN I VIN2 MAX (RDR )(CMILLER ) * 2 1 1 + ( f) VCC - VTH(IL) VTH(IL) V -V PSYNC = IN OUT (IMAX )2(1+ )RDS(0N) VIN PMAIN = where is the temperature dependency of RDS(ON), RDR is the effective top driver resistance, VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve. Typical LTC3860 applicaTions inFormaTion 2. Transition losses apply only to the topside MOSFET but in 12V input applications are a very significant source of loss. They can be minimized by choosing a driver with very low drive resistance and choosing a MOSFET with low QG, RG and CRSS. 3. Gate drive current is equal to the sum of the top and bottom MOSFET gate charges multiplied by the frequency of operation. However, many drivers employ a linear regulator to reduce the input voltage to a lower gate drive voltage. This multiplies the gate loss by that step down ratio. In high frequency applications it may be worth using a secondary user supplied rail for gate drive to avoid the linear regulator. Other sources of loss include body or schottky-diode conduction during the driver dependent non-overlap time and inductor core losses. Design Example As a design example, consider a 2-phase application where VIN = 12V, VOUT = 1.2V, ILOAD = 50A and fSWITCH = 600kHz. Assume that a secondary 5V supply is available for the LTC3860 VCC supply. The inductance value is chosen based on a 30% ripple assumption. Each channel supplies an average 25A to the load resulting in 7.5A peak-peak ripple: V VOUT * 1 - OUT VIN IL = f *L A 240nH inductor per phase will create 7.5A peak-to-peak ripple. A 0.3H inductor with a DCR of 0.7m typical is selected from the Vishay IHLP5050FD-01 series. Connect CLKIN to SGND and FREQ to VCC to select 600kHz operation. Setting ILIMIT = 50A per phase leaves plenty of headroom for transient conditions while still adequately protecting against inductor saturation. This corresponds to: RILIM = 18.5 * 50 A * 0.7m + 0.55V = 59.9k 20A Choose 60.4k. For the DCR sense filter network, we can choose R = 2.0k and C = 220nF to match the L/DCR time constant of the inductor. A loop crossover frequency of 100kHz provides good transient performance while still being well below the switching frequency of the converter. Four 330F 9m POSCAPs are chosen for the output capacitors to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. The following compensation values (Figure 12) were determined empirically: R1 = 10k R2 = 6.04k R3 = 698 C1 = 680pF C2 = 47pF C3 = 390pF To set the output voltage equal to 1.2V: RB = 10k The Renesas R2J20601NP integrated-driver MOSFET is chosen for the power stages because of its high efficiency 3860f LTC3860 applicaTions inFormaTion and high level of integration. Printed Circuit Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter. 1. The connection between the SGND pin on the LTC3860 and all of the small-signal components surrounding the IC should be isolated from the system power ground. Place all decoupling capacitors, such as the ones on VCC, between ISNSP and ISNSN etc., close to the IC. In multiphase operation SGND should be Kelvin-connected to the main ground node near the bottom terminal of the input capacitor. In dual-channel operation, SGND should be Kelvin-connected to the bottom terminal of the output capacitor for channel 2, and channel 1 should be remotely sensed using the remote sense differential amplifier. 2. Place the small-signal components away from high frequency switching nodes on the board. The LTC3860 contains remote sensing of output voltage and inductor current and logic-level PWM outputs enabling the IC to be isolated from the power stage. 3. The PCB traces for remote voltage and current sense should avoid any high frequency switching nodes in the circuit and should ideally be shielded by ground planes. Each pair (VSNSP and VSNSN, ISNSP and ISNSN) should be routed parallel to one another with minimum spacing between them. If DCR sensing is used, place the top resistor (Figure 6b, R1) close to the switching node. 4. The input capacitor should be kept as close as possible to the power MOSFETs. The loop from the input capacitor's positive terminal, through the MOSFETs and back to the input capacitor's negative terminal should also be as small as possible. 5. If using discrete drivers and MOSFETs, check the stress on the MOSFETs by independently measuring the drainto-source voltages directly across the device terminals. Beware of inductive ringing that could exceed the maximum voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET. 6. When cascading multiple LTC3860 ICs, minimize the capacitive load on the CLKOUT pin to minimize phase 3860f Dual Output with DRMOS DRMBIAS1 4.7F 1F VOS1P VCIN VIN R2J20601 VSWH PGND 2.74k VLDRV 4.7F OPEN (OPT) SW1 0.3H 47 47F 3 330F 3 47 VOS1N REG5V BOOT DRMDISABLE VCC 20k 100k 49.9k PWM1 OPEN CGND VCC DISABLE PWM 0.22F VOUT2 20k 100pF 22F 2.2 VIN VIN 7V TO 14V 470F Typical applicaTions VOUT1 1.2V 25A RUN1 VCC 5V 1F 1000pF 0.22F 0.22F 49.9k VDRIVE 20k 220 LTC3860 47pF 20k 4.7k 470pF VDIFF1 VOS1N VOS1P SGND PWMEN1,2 FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWM2 1000pF VOUT2 PWM2 VCC OPEN (OPT) OPEN (OPT) 4.7F DRMBIAS2 2.2 CGND PWM DISABLE VCIN 0.1F 45.3k 100k VCC 20k 220 47pF VCC TRACK/SS1 VINSNS IAVG PGOOD1 PWM1 RUN1 VDIFF1 4.7F VLDRV R2J20601 VIN VIN 22F PGND VSWH REG5V BOOT SW2 2.74k 0.3H 47F 3 0.22F 330F 3 3860 TA02 10k 4.7k 470pF FREQ SET FOR 600kHz CLKOUT VOUT2 1.8V 25A RUN2 7V TO 14V IN AND 1.2V/1.8V OUT AT 25A fSW = 600kHz, DCR SENSING CH1 TRACKS CH2, CH1 USES DIFFAMP NOTE 1: PLEASE REFER TO THE R2J20601 DATA SHEET FOR THE MOST UP TO DATE PINOUT NOTE 2: PLEASE REFER TO THE PIN CONFIGURATION OF THIS DATA SHEET FOR THE LTC3860 PINOUT 1F LTC3860 3860f LTC3860 Typical applicaTions Quad-Phase Single Output with DRMOS VIN 7V TO 14V DRMBIAS1 470F TRACK/SS1 0.01F RUN1 VCC 5V VCC I AVG1 100k 100pF PWM1 1F TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 VCC OPEN (OPT) DRMDISABLE 2.2 4.7F VCIN VIN REG5V BOOT VSWH PGND 4.7F VDRIVE 0.22F SW1 0.4H 2k 1F 22F VIN DISABLE R2J20601 PWM CGND VLDRV OPEN (OPT) 49.9k 0.22F 0.22F 1000pF VDIFF 20k 20k 220 COMP1 47pF 470pF VDIFF VOSN VOSP VCC 4.7k TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 LTC3860 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VCC RUN1 VCC VDRIVE 4.7F TRACK/SS1 VCC PWM2 OPEN (OPT) OPEN (OPT) CGND VLDRV PGND VSWH BOOT SW2 2k 0.4H PWM R2J20601 DISABLE VCIN 4.7F VIN REG5V 0.22F 1F VOSP 47 47F 6.3V 8 330F 2.5V 8 47 VOSN VOUT1 1.2V 100A DRMBIAS2 2.2 22F VIN VIN 7V TO 14V DRMBIAS3 470F VCC OPEN (OPT) RUN1 1F TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 49.9k 0.22F 0.22F VDRIVE DRMDISABLE 2.2 4.7F VCIN VIN REG5V BOOT VSWH PGND 4.7F 0.22F SW3 0.4H 2k 1F 22F VIN TRACK/SS1 VCC 5V IAVG1 PWM3 DISABLE R2J20601 PWM CGND VLDRV OPEN (OPT) VCC VCC TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 LTC3860 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VCC RUN1 VCC VDRIVE 4.7F TRACK/SS1 45.3k PWM4 OPEN (OPT) OPEN (OPT) CGND VLDRV PGND VSWH BOOT SW4 2k 0.4H 3860 TA03 PWM R2J20601 DISABLE VCIN 4.7F VIN REG5V 22F 0.22F 1F DRMBIAS4 2.2 VIN 3860f 0 Dual-Phase Single Output with Discrete Drivers and MOSFETs VIN 7V TO 14V 100pF 22F 2 RJK0305DPB BG1 TG1 SW1 RJK0330DPB RJK0330DPB 2.74k 0.22F SW1 0.22F 0.22F VIN 22F 2 RJK0305DPB BG2 TG2 RJK0330DPB RJK0305DPB SW2 RJK0330DPB 0.3H 5 0.3H 47F 3 RJK0305DPB 5 VIN 470F TRACK/SS1 VCC 100k 49.9k PWM1 VCC 4.7F 2.2 6 7 8 0.1F 1F VOS1P 47 330F 3 47 VOS1N VOUT1 1.2V 50A Typical applicaTions RUN1 VCC 5V LTC4449 4 IN GND 3 VLOGIC BG 2 VCC TS 1 BOOST TG 1F 1.5nF 20k 1.33k LTC3860 VCC 33pF 20k TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWM2 220pF 12.7k VDIFF1 VOS1N VOS1P VCC SGND PWMEN1,2 FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VCC TRACK/SS1 VINSNS IAVG PGOOD1 PWM1 RUN1 VDIFF1 2.74k SS1 45.3k 4.7F VCC 0.22F SW2 2.2 PWM2 1F LTC4449 4 IN GND 3 6 VLOGIC BG 2 7 VCC TS 1 8 BOOST TG 3860 TA04 47F 3 330F 3 FREQ SET FOR 600kHz CLKOUT RUN2 7V TO 14V IN AND 1.2V OUT AT 50A fSW = 600kHz, DCR SENSING NOTE: PLEASE REFER TO THE PIN CONFIGURATION OF THIS DATA SHEET FOR THE LTC3860 PINOUT LTC3860 3860f LTC3860 Typical applicaTions Dual Output--3-Channel + Single Channel, Sychronized to External Clock VIN 7V TO 14V DRMBIAS1 470F TRACK/SS1 0.01F RUN1 VCC 5V VCC IAVG1 100pF PWM1 1F TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 VCC OPEN (OPT) DRMDISABLE 2.2 4.7F VCIN VIN REG5V BOOT VSWH PGND 4.7F VDRIVE 0.22F SW1 0.3H 2.3k 1F 22F VIN 100k DISABLE R2J20601 PWM CGND VLDRV OPEN (OPT) 49.9k 0.22F 0.22F 1000pF VDIFF1 20k 20k 220 COMP1 47pF 470pF VDIFF VOSN VOSP VCC 4.7k TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 LTC3860 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VCC RUN1 VCC VDRIVE 4.7F 2.3k SW2 0.3H VOSP 47 47F 6.3V 6 VOUT1 1.2V 330F 75A 2.5V 6 47 VOSN 2.2 4.7F 0.22F 1F 0.3H VCIN VIN REG5V BOOT VSWH PGND 4.7F VDRIVE SW3 VIN 22F VIN CLOCKIN 600kHz SYNC INPUT TRACK/SS1 PWM2 45.3k OPEN (OPT) OPEN (OPT) CGND VLDRV PGND VSWH BOOT PWM R2J20601 DISABLE VCIN 4.7F VIN REG5V 0.22F 1F DRMBIAS2 2.2 22F VIN 7V TO 14V DRMBIAS3 470F VCC DRMDISABLE TRACK/SS1 IAVG1 PWM3 RUN1 1F TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 49.9k 0.22F 0.22F 49.9k VCC OPEN (OPT) OPEN (OPT) OPEN (OPT) OPEN (OPT) DISABLE R2J20601 PWM CGND VLDRV VCC 5V 2.32k 1000pF 220 VDIFF4 VCC COMP1 20k 10k VOS4P 47pF VOS4N 470pF 4.7k TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 LTC3860 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VDRIVE 4.7F 2.32k SW4 0.3H VOS4P 47 47F 3 VOUT4 1.8V 330F 25A 3 47 VOS4N VIN 3860 TA05 0.01F 45.3k 100k VCC PWM4 CGND VLDRV PGND VSWH BOOT PWM R2J20601 DISABLE VCIN 4.7F VIN REG5V RUN2 0.22F 1F DRMBIAS4 2.2 22F 3860f 2-Phase 1.5V/40A Converter with Delta 20A Power Blocks and External 400kHz Clock VIN 7V TO 14V 100pF TRACK/SS1 100k OPEN OPT PWM1 OPEN OPT 10 1nF 10 1nF 10 10 5V BIAS VCC OPEN OPT PWM2 34.8k OPEN OPT 22F D12S36A 22F VIN 22F 100k VCC 22F VIN VCC 5V BIAS 10k IAVG1 Typical applicaTions 470F 0.1F RUN1 2200pF LTC3860 VCC RUN1 TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 VCC 5V 1F D12S36A 5V VIN GND2 ENABLE CSP PWM CSN TEMP VOUT GND1 100F 6.3V VOSP 47 VOUT 1.5V 40A 330F 2.5V 6 47 VOSN VDIFF COMP1 20k 523 100pF VDIFF VOSN VOSP TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 13.3k 6.8k 470pF VCC VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 CLOCKIN 400kHz SYNC INPUT TRACK/SS1 5V VIN GND2 ENABLE CSP PWM CSN TEMP VOUT GND1 3860 TA06 100F 6.3V 10k LTC3860 3860f LTC3860 Typical applicaTions 2200pF 1nF 10 1nF 10 100k 7V BIAS VCC PWM2 0.1F VCC 34.8k 100k OPEN OPT OPEN OPT 1F 10 LTC3860 VCC TRACK/SS1 VINSNS IAVG PGOOD1 PWM1 RUN1 2200pF VOUT2 TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWM2 Dual Output Converter with Artesyn 30A (SMT30PB-OISADJJ) Power Blocks 0 0.1F 7V BIAS VCC PWM1 OPEN OPT 10 100k OPEN OPT 1F 22F VIN 100k VCC VOS1P 51 100F 2 330F 3 51 VOS1N VOUT1 1V 25A GND ARTESYN 30A 7V VIN VOUT TEMP CSP PWM CSN GND SGND PWMEN1,2 FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 22F VIN ARTESYN 30A 7V VIN VOUT TEMP CSP PWM CSN GND 3860 TA07 VIN 8V TO 14V 470F RUN1 VCC 5V 1F VDIFF1 20k 523 100pF VDIFF1 VOS1N VOS1P 29.4k 6.8k 470pF 20k 523 100pF 100F 2 330F 3 VOUT2 1.8V 25A GND 10k 6.8k 470pF RUN2 8V TO 14V IN AND 1.0V/1.8V OUT AT 25A fSW = 400kHz CH1 USES DIFFAMP 3860f LTC3860 package DescripTion (Reference LTC DWG # 05-08-1693 Rev D) UH Package 32-Lead Plastic QFN (5mm x 5mm) 0.70 0.05 5.50 0.05 4.10 0.05 3.50 REF (4 SIDES) 3.45 0.05 3.45 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 45 CHAMFER 31 32 0.40 1 2 3.45 0.10 0.10 3.50 REF (4-SIDES) 3.45 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC 3860f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC3860 Typical applicaTion Dual Phase Single Output with DRMOS and RSENSE VIN 7V TO 14V DRMBIAS1 470F TRACK/SS1 0.01F RUN1 VCC 5V VCC IAVG1 100pF PWM1 1F TRACK/SS1 VINSNS SGND SGND IAVG PGOOD1 PWMEN1 PWM1 VCC OPEN (OPT) DRMDISABLE 2.2 4.7F VCIN VIN REG5V BOOT VSWH PGND 4.7F 100 VDRIVE 0.22F SW1 0.3H 1F 1m 22F VIN 100k DISABLE R2J20601 PWM CGND VLDRV OPEN (OPT) 59.0k 0.01F 0.01F 1000pF VDIFF1 20k 20k 220 COMP1 47pF 470pF VDIFF VOSN VOSP VCC 4.7k TRACK/SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2 VCC FB1 COMP1 VSNSOUT VSNSN VSNSP COMP2 FB2 LTC3860 RUN1 ILIM1 ISNS1P ISNS1N ISNS2N ISNS2P ILIM2 RUN2 VCC RUN1 VCC VDRIVE 4.7F VOSP CGND VLDRV PGND VSWH BOOT SW2 0.3H 1m PWM R2J20601 DISABLE VCIN 4.7F VIN REG5V 47 47F 6.3V 4 VOUT1 1.2V 330F 40A 2.5V 4 47 VOSN VIN 3860 TA08 CLOCKIN 600kHz SYNC INPUT TRACK/SS1 PWM2 45.3k OPEN (OPT) OPEN (OPT) 0.22F 1F DRMBIAS2 2.2 22F relaTeD parTs PART NUMBER DESCRIPTION COMMENTS Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V VIN 30V, 0.8V VOUT 5.25V Phase-Lockable Fixed Frequency 250kHz to 770kHz, 4.5V VIN 38V, 0.8V VOUT 12.5V Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V VIN 24V, VOUT3 Up to 13.5V LTC3850/LTC3850-1 Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC LTC3850-2 Controller, RSENSE or DCR Current Sensing and Tracking LTC3855 LTC3853 LTC3775 LTC3878 LTC3879 LTC4442 LTC4449 Dual, Multiphase, Synchronous DC/DC Step-Down Controller with Diffamp and DCR Temperature Compensation Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking High Frequency Synchronous Voltage Mode Step-Down DC/DC Fast Transient Response, tON(MIN) = 30ns, 4V VIN 38V, Controller 0.6V VOUT 0.8VIN, MSOP-16E, 3mm x 3mm QFN-16 No RSENSETM Constant On-Time Synchronous Step-Down Very Fast Transient Response, tON(MIN) = 43ns, 4V VIN 38V, DC/DC Controller, No RSENSE Required 0.8V VOUT 0.9VIN, SSOP-16 No RSENSE Constant On-Time Synchronous Step-Down DC/DC Controller, No RSENSE Required High Speed Synchronous N-Channel MOSFET Driver High Speed Synchronous N-Channel MOSFET Driver Very Fast Transient Response, tON(MIN) = 43ns, 4V VIN 38V, 0.6V VOUT 0.9VIN, MSOP-16E, 3 x 3 QFN-16 VIN Up to 38V, Adaptive Shoot-Through Protection, 2.4A Pull-up Current, 5A Pull-Down Current VIN Up to 38V, Adaptive Shoot-Through Protection, 3.2A Pull-up Current, 4.5A Pull-Down Current 3860f Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 LT 0210 * PRINTED IN USA www.linear.com LINEAR TECHNOLOGY CORPORATION 2010 |
Price & Availability of LTC3860
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |